The present invention relates generally to memory systems, and more specifically, to scrubbing of memory systems.
Dynamic random access memories (DRAMs) experience occasional errors during memory reads and writes, both correctable (soft) errors and uncorrectable (hard) errors. Memory systems using DRAMs include hardware such as symbol or device-based error correcting code (ECC) circuitry, memory mirroring, redundant array of independent memory (RAIM) ECC, scrubbing, marking, sparing, and retries. When scrubbing and/or marking are implemented, counters are often utilized to record detected errors and determine the type of error encountered.
Scrubbing and marking hardware is often tested using verification models. However, it is difficult to model all the code paths so it may be more desirable to test the final hardware and software together to test for defects. Even so, it may not be practical to build hardware that will contain all possible device failures. Therefore, programmable error injection hardware can be used to cover these error scenarios. To insert injection hardware at the DRAMs or dual in-line memory modules (DIMMs) or buffer chips can be expensive. Also, in a RAIM type system, each component (e.g. buffer chip or DRAMs) has no information about first or second scrub passes as well as data types. On the other hand, the memory controller and/or host processor include ECC and cyclic redundancy check (CRC) features, as well as asynchronous paths which often hinder the ability to mimic a soft versus hard error.